Teledyne LeCroy has introduced the DDR Debug Toolkit for complete physical layer analysis of DDR 2/3/4 and LPDDR2/3 signals. Most oscilloscope-based DDR physical layer test tools on the market are ...

You all write code and then toil to makeit work. You build it, and then you fixit. Testing is an afterthought—somethingyou do after you write the code.You spend about half your time in ...

TOKYO, May 08, 2025 (GLOBE NEWSWIRE) -- Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857) today unveiled SiConic Test Engineering (TE), the newest addition to the SiConic ...

In increasingly complex SoC designs, many of which contain multiple cores and multiple modes, determining best practices for testing and debugging is a moving target. Jason Andrews, architect at ...

ANAHEIM, Calif. — At an open meeting held Monday at the Design Automation Conference, EDA, test and silicon debug companies announced the creation of the Design-for-Debug (DFD) Consortium to address ...

With each turn of Moore's Law, designers at every phase in the development process are challenged with new levels of complexity. Chip designers must not only get the integrated circuit (IC) logic, ...

Mentor, a Siemens business, has announced the availability of the ATE-Connect technology in its Tessent SiliconInsight product for IC debug and bring up. The ATE-Connect technology creates an industry ...

As Moore's Law steams ahead, the resulting rush to retool for ever-smaller geometries has led to the realization by most leading companies designing systems-on-chip that the emphasis in SoCs is on ...

Advantest Corp. has unveiled SiConic Test Engineering (TE), the newest addition to the SiConic family introduced in February 2025. SiConic TE offers test engineers the ability to bring up and validate ...

There appears to be an unwritten law about the time spent in debug-it is a constant. It could be that all gains made by improvements in tools and methodologies are offset by increases in complexity, ...